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XC6VHX380T-2FF1155I******可编程FPGA

时间:2019-7-10,阅读:171,发布企业:北京显易科技有限公司, 资讯类别:会员资讯
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北京显易科技有限公司
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General Description


The Virtex®-6 family provides the newest, most advanced features in the FPGA market. Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. Using the third-generation ASMBL™ (Advanced Silicon Modular Block) column-based architecture, the Virtex-6 family contains multiple distinct sub-families. This overview covers the devices in the LXT, SXT, and HXT sub-families. Each sub-family contains a different ratio of features to most efficiently address the needs of a wide variety of advanced logic designs. In addition to the high-performance logic fabric, Virtex-6 FPGAs contain many built-in system-level blocks. These features allow logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 40 nm state-of-the-art copper process technology, Virtex-6 FPGAs are a programmable alternative to custom ASIC technology. Virtex-6 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, connectivity, and soft microprocessor capabilities.



Summary of Virtex-6 FPGA Features


0 Three sub-families:


0 Virtex-6 LXT FPGAs: High-performance logic with advanced serial connectivity

0 Virtex-6 SXT FPGAs: Highest signal processing capability with advanced serial connectivity


0 Virtex-6 HXT FPGAs: Highest bandwidth serial connectivity


0 Compatibility across sub-families


0 LXT and SXT devices are footprint compatible in the same package

0 Advanced, high-performance FPGA Logic


0 Real 6-input look-up table (LUT) technology

0 Dual LUT5 (5-input LUT) option

0 LUT/dual flip-flop pair for applications requiring rich register mix

0 Improved routing efficiency

0 64-bit (or two 32-bit) distributed LUT RAM option per 6-input LUT

0 SRL32/dual SRL16 with registered outputs option


0 Powerful mixed-mode clock managers (MMCM)


0 MMCM blocks provide zero-delay buffering, frequency synthesis, clock-phase shifting, input-jitter filtering, and phase-matched clock division

0 36-Kb block RAM/FIFOs


0 Dual-port RAM blocks

0 Programmable

0 Dual-port widths up to 36 bits

0 Simple dual-port widths up to 72 bits

0 Enhanced programmable FIFO logic

0 Built-in optional error-correction circuitry

0 Optionally use each block as two independent 18 Kb blocks

0 High-performance parallel SelectIO technology


0 1.2 to 2.5V I/O operation

0 Source-synchronous interfacing using ChipSync™ technology

0 Digitally controlled impedance (DCI) active termination

0 Flexible fine-grained I/O banking

功耗最低的128宏单元CPLD
6.0 ns的引脚对引脚的逻辑延迟
系统频率高达145 MHz的
128个宏单元3000可用门
可在小型封装
- 144引脚TQFP ( 108个用户I / O引脚)
- 144球BGA CS ( 108个用户I / O)
- 100引脚VQFP ( 84个用户I / O)
优化3.3V系统
- 超低功耗运行
- 5V容限I / O引脚3.3V内核电源
- 先进的0.35微米五层金属EEPROM
过程
- 快速零功率 ( FZP ) CMOS设计
技术
先进的系统功能
- 在系统编程
- 输入寄存器
- 可预测的时序模型
- 最多每个功能块23可用的时钟
- 在设计变更优秀销固定
- 完整的IEEE标准1149.1边界扫描( JTAG )
- 四个全局时钟
- 每个功能块八乘积项控制项
快速ISP编程时间
端口使能引脚额外的I / O
2.7V至在工业温度3.6V电源电压
范围
每路输出可编程转换速率控制
安全位可以防止未经授权的访问
请参阅XPLA3系列数据表( DS012 )的
体系结构描述


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